Layout-accurate Ultra-fast System-level Design Exploration through Verilog-ams

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution. Song Fu, for reviewing my progress and my dissertation, and for providing inspirational suggestions. I would like thank all my labmates at the NanoSystem Design Laboratory (NSDL, http://nsdl.cse.unt.edu), including, Oleg, Karo, and Mahesh for their help and collaboration. I would like to extend my appreciation to the staff of the Department of Computer Science and Engineering for their very helpful support. Special thanks to my mother Xingying Chen and my father Wanfa Zheng. Words cannot express my gratitude for their support, help, and sacrifices. Last but not the least, I would like to thank all my friends who have supported me throughout.